The present invention relates to semiconductor devices and, more particularly, to synchronous semiconductor memory devices having a delay locked loop (DLL).
Because a synchronous semiconductor device operated in synchronization with an external clock generates an internal clock using a clock buffer and a clock driver, an internal clock within the synchronous semiconductor device is normally delayed as much as a predetermined delay time with respect to the external clock buffer. This delay decreases operating efficiency of the semiconductor device. In particular, the data access time (tAC) of the semiconductor device increases as much as the predetermined delay time due to the clock buffer or the like inside the chip. Accordingly, an internal clock generation circuit, which generates the internal clock synchronized with the external clock, is required inside the synchronous semiconductor device within the chip. At this time, a delay locked loop is used as the internal clock generation circuit to synchronize the internal and external clock signals.
Referring to FIG. 1, a conventional delay locked loop includes a clock buffer 10, a voltage controlled delay line 20, an output buffer 80, a data strobe signal output buffer 70, a replica delay 40, a phase detector 30, a charge pump 50 and a loop filter 60. In operation, the clock buffer 10 receives the external clock and the voltage controlled delay line 20 delays the output of the clock buffer 10 as much as the predetermined time. The data output buffer 80 outputs data outputted from a DRAM core according to the output of the voltage controlled delay line 20 and the data strobe signal output buffer 70 receives the output of the voltage controlled delay line 20 and outputs a data strobe signal.
The replica delay 40 monitors delay time of the clock buffer 10 and the data output buffer 80 and the phase detector 30 receives the output of the replica delay 40 and the output of the clock buffer 10 and compares phases thereof. The charge pump 50 and the loop filter 60 adjust the delay of the voltage controlled delay line 20 according to the output of the phase detector 30. The data output buffer 80 and the data strobe signal output buffer 70 are designed to have the same delay (Td).
Now, an operation of the delay locked loop will be described with reference to FIG. 1.
The external clock (ext_clk) is buffered in the clock buffer 10 and inputted into the phase detector 30 through the voltage controlled delay line 20 and the replica delay 40. The phase detector 30 compares the output of the clock buffer 10 with the output of the replica delay 40 and the charge pump 50 and the loop filter 60 adjust delay of the voltage controlled delay line 20 according to the comparison result in the phase detector 30. The above process is repeated so that two input values of the phase detector 30 are phase-locked. After the two input values of the phase detector 30 are phase-locked, the clock outputted from the voltage controlled delay line 20 is used as the internal clock synchronized with the external clock. The output buffer 80 outputs data according to the synchronized internal clock.
When considering a procedure by which the internal clock is synchronized with the external clock, a clock, which is as fast as and has a delay time generated by the clock buffer 10 and the data output buffer 80, is generated. The internal clock synchronized with the external clock is generated by the voltage controlled delay line 20 and passes to the data output buffer 80. Accordingly, the replica delay 40 is designed to have delay time identical to sum of the delay time (Ta) in the clock buffer 10 and the delay time (Td) in the data output buffer 80.
However, it is practically impossible that the delay time in the replica delay 40 is accurately accorded with the sum of the delay time (Ta) in the clock buffer 10 and the delay time (Td) in the data output buffer 80. Due to some problems of a process environment, such as pressure, voltage, temperature or the like and a package process, that the internal clock is not accurately synchronized with the external clock and has a fixed offset after phase locking.
Referring to FIG. 2, the internal clock is outputted with a fixed offset for the external clock. It is generally called as a clock skew. The clock skew is shown at xe2x80x98Axe2x80x99 denoted in FIG. 2. As mention the above, because the outputs of the clock buffer 10 and the data output buffer 80 and the outputs of the clock buffer replicated in the replica delay 40 and the data output buffer 80 are mismatched, clock skew is generated. Also, clock skew can be generated by a process environment or package. Accordingly, a process for adjusting the internal clock so that it is accurately synchronized with the external clock is required after manufacturing the semiconductor memory device.
Generally, there are two methods used to adjust delay time. A first method is to adjust delay time of the replica delay on a wafer and a second method is to adjust delay time of the replica delay after the semiconductor device is packaged.
FIG. 3A is block diagram illustrating a delay locked loop capable of adjusting delay time of the replica delay 40 on a wafer according to the prior art.
Referring to FIG. 3A, when adjusting delay time of the replica delay 40 on the wafer level, a fuse unit 41 is provided at the replica delay 40 and a phase offset of the internal clock synchronized with the external clock is measured after phase locking. The fuses are blown by a laser to adjust the replica delay 40 to be as much as the measured phase offset. At this time, expensive laser equipment is required to adjust blowing of fuse unit 41 and, even if the internal clock is synchronized with the external clock by minimizing the phase offset, the operation can be changed after the packaging process.
Referring to FIG. 3B, when adjusting delay time of the replica delay 40 after the package is completed, an anti-fuse unit 42 is equipped at the replica delay 40 and the anti-fuse is shorted as much as phase offset of the internal clock. At this time, high voltage is applied into a specific input pin and an insulator of the anti-fuse unit 42 breaks down so that the anti-fuse unit 42 is shorted. Accordingly, expensive laser equipment used for adjusting delay time at the wafer is not required and an error generated in the real operation is minimized because the adjustment of the phase offset is performed after the package is completed.
However, it is disadvantageous that the specific pin for applying the high voltage is used not at a real operation but just as delay time adjustment. Also, if the high voltage is applied from the exterior, it has a bad effect on reliability of other devices.
In accordance with an aspect of the disclosed apparatus, there is provided a synchronous semiconductor device having a delay locked loop that may include a replica delay for replicating delay time of an internal circuit, an anti-fuse circuit for controlling the replicated delay time, and a voltage generator for applying voltage into the anti-fuse circuit.
In accordance with another aspect of the disclosed apparatus, there is provided a semiconductor device that may include a clock buffer for receiving an external clock signal and generating an internal clock signal, a delay line for delaying the internal clock signal for synchronization with the external clock signal, and an output buffer for receiving an output of the delay line and outputting the internal clock signal. The semiconductor device may also include a replica delay for receiving the output of the delay line, replicating delay time until the external clock signal is outputted as the internal clock signal and adjusting the replicated delay time and a phase detector for comparing the output phase of the replica delay with the output phase of the clock buffer. Further, the semiconductor device may include a phase control unit for controlling delay time of the delay line in response to an output signal of the phase detector, an anti-fuse circuit for outputting a control signal to adjust the replicated delay time and a voltage generator for applying voltage into the anti-fuse circuit.